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The multicore shared memory controller allows access to shared and external memory directly without drawing from switch fabric capacity.įor fixed-point use, the C66x core has 4× the multiply accumulate (MAC) capability of C64x+ cores. The TeraNet is a nonblocking switch fabric enabling fast and contention-free internal data movement. Central to this architecture are key components such as Multicore Navigator that allows for efficient data management between the various device components. TI’s KeyStone architecture provides a programmable platform integrating various subsystems (C66x cores, memory subsystem, peripherals, and accelerators) and uses several innovative components and techniques to maximize intradevice and interdevice communication that lets the various DSP resources operate efficiently and seamlessly. In addition, the C665x DSPs are fully backward compatible with all existing C6000™ family of fixed- and floating-point DSPs. For developers of a broad range of applications, both C665x DSPs enable a platform that is power-efficient and easy to use. Incorporating the new and innovative C66x DSP core, this device can run at a core speed of up to 1.25 GHz. The C665x are high performance fixed- and floating-point DSPs that are based on TI’s KeyStone multicore architecture. Two Multichannel Buffered Serial Ports (McBSPs).Supports Connections to Other KeyStone Architecture Devices Providing Resource Scalability.Supports Four 1×, Two 2×, One 4×, and Two 1× + One 2× Link Configurations.1.24, 2.5, 3.125, and 5 GBaud Operation Supported Per Lane.Packet-Based DMA for Zero-Overhead Transfers.8192 Multipurpose Hardware Queues with Queue Manager.Memory Protection Unit for Both MSM SRAM and DDR3_EMIF.

(Shared by Two DSP C66x CorePacs for C6657) Multicore Shared Memory Controller (MSMC).20 GFLOP per Core for Floating Point 1.25 GHz.40 GMAC per Core for Fixed Point 1.25 GHz.850 MHz (C6657 only), 1.0 GHz, or 1.25 GHz C66x Fixed- and Floating-Point CPU Core.One (C6655) or Two (C6657) TMS320C66x™ DSP Core Subsystems (CorePacs), Each With.